1. Field of the Invention
The present invention relates to a synchronous semiconductor memory device which takes in an external signal in synchronization with an externally and periodically supplied clock signal, and in particular to a structure of a data writing portion in a synchronous dynamic random access memory (SDRAM) allowing random access.
2. Description of the Background Art
In processing systems, operation speeds of dynamic random access memories used as main memories have been increased, but are still low compared with operation speeds of microprocessors (MPUs). It has often been reported that the above fact increases a wait time of the microprocessor, and impedes fast processing, as an access time and a cycle time of the DRAM form a bottleneck in a whole system performance. In order to eliminate a difference in operation speed between the DRAM and the microprocessor, clock synchronous semiconductor memory devices which operate in synchronization with a clock signal have recently been developed, and SDRAMs have been used as main memories for fast microprocessors.
In this SDRAM, take-in of external signals, i.e., address signals and control signals as well as input/output of data are performed in synchronization with a clock signal which is, for example, a system clock. Since the external signals are taken into the device in synchronization with the clock signal, it is not necessary to take a margin for skew of these external signals into consideration, and an internal operation can be started rapidly. Since input and output of data take place in synchronization with the clock signal, the access speed of data corresponds to the clock signal, so that fast data transmission is allowed.
In this SDRAM, continuous bits (e.g., eight bits per data I/O terminal) are continuously accessed in synchronization with the clock signal in order to achieve fast access.
FIG. 37 is a timing chart showing an operation for data reading in an SDRAM. In the SDRAM, operation modes are determined by combinations of states of external control signals /RAS, /CAS and /WE at rising edges of an external clock signal extCLK. The combinations of the states of the external control signals are generally called commands. Signal /RAS is a row address strobe signal, and signal /CAS is a column address strobe signal. Signal /WE is a write enable signal.
In a clock cycle #1 of external clock signal extCLK (which will be merely called a "clock cycle" hereinafter) in FIG. 37, row address strobe signal /RAS is set to L-level, and column address strobe signal /CAS and write enable signal /WE are both set to H-level at a rising edge of external clock signal extCLK. The combination of these states of signals /RAS, /CAS and /WE is called an "active command", which instructs start of the memory cycle in the SDRAM. When this active command is applied, the device takes in a currently applied address signal Add as a row address signal Xa, and internally performs a row select operation. When a delay time tRCD, which is generally called an RAS-CAS delay time in a standard DRAM, elapses after the application of this active command, a command for column selection is applied.
More specifically, at the rising edge of external clock signal extCLK in a clock cycle #4, row address strobe signal /RAS and write enable signal /WE are set to H-level, and column address strobe signal /CAS is set to L-level. The combination of these states of signals /RAS, /CAS and /WE is called a "read command", which instructs a data read operation together with the column selection. When this read command is applied, the device takes in currently applied address signal Add as a column address signal Yb, and performs the column selection. A certain time is required till data in a selected memory cell reaches an output circuit for outputting the data. When this time elapses, first data q0 is fixed at the rising edge of external clock signal extCLK in a clock cycle #7. Thereafter, read data q1-q7 are made definite at rising edges of external clock signal extCLK in clock cycles #8-#14, respectively.
Addresses of data q0-q7 are automatically generated in the SDRAM with column address signal Yb as a leading address. (The addresses generated in this manner are called burst addresses.) The number of cycles of external clock signal extCLK from application of the read command to first output of valid data is called a CAS latency. In FIG. 37, the CAS latency is 3.
The number of bits of data (per one data I/O terminal) which are read continuously in response to one read command is called a burst length. FIG. 37 shows a data read sequence in the case where the burst length is 8. In the SDRAM, the CAS latency and the burst length can be changed by data set in a mode register.
FIG. 38 shows a data write sequence of the SDRAM. A data write operation will be described below with reference to FIG. 38.
In clock cycle #1, and particularly at the rising edge of external clock signal extCLK, signal /RAS is set to L-level, and signals /CAS and /WE are both set to H-level. Thereby, the active command is applied, and the device takes in the currently supplied address signal Add as a row address signal Xc and internally performs the row select operation.
At the rising edge of external clock signal extCLK in clock cycle #4, row address strobe signal /RAS is set to H-level, and column address strobe signal /CAS and write enable signal /WE are both set to L-level. The combination of these states of signals /RAS, /CAS and /WE is called a "write command", which instructs data writing together with the column selection. When this write command is applied, the device takes in currently applied address signal Add as column address signal Yd, and internally performs the column selecting operation.
In the data write operation, the CAS latency is not required, and the device starts take-in of external write data in clock cycle #4. More specifically, in clock cycle #4 in which the write command is applied, the device takes in data d0 in synchronization with the rising of external clock signal extCLK, and applied write data d1-d7 are successively taken in at the rising edges of external clock signal extCLK in subsequent clock cycles #5-#11, respectively. These data d0-d7 are internally written into selected memory cells in accordance with a predetermined sequence, respectively.
During this data writing, take-in of data starts from the clock cycle in which the write command is applied. Actual writing into the selected memory cell is slightly delayed as will be described later (because a time is required for data transmission through a write path from an input buffer stage to the selected memory cell). As shown in FIGS. 37 and 38, write/read of data are performed in synchronization with external clock signal extCLK, and therefore input/output of data can be performed in synchronization with, e.g., the system clock determining the operation speed of the microprocessor, so that fast access is allowed.
In the SDRAM, transmission of internal data is performed in synchronization with the clock signal (i.e., internal clock signal produced from the external clock signal). A 2-bit prefetch method and a pipeline method have been known architectures for implementing the above SDRAM. These methods will be described below.
FIG. 39 schematically shows a structure of a portion related to one data I/O terminal in an SDRAM employing the 2-bit prefetch method. The structure shown in FIG. 39 is provided corresponding to each of data I/O terminals.
In FIG. 39, the SDRAM includes memory arrays 1aa, 1ab, 1ba and 1bb each having a plurality of memory cells arranged in rows and columns. The SDRAM has two banks A and B. Memory arrays 1aa and 1ab form bank A, and memory arrays 1ba and 1bb form bank B. In banks A and B, memory array 1aa forms a subbank A0, memory array 1ab forms a subbank A1, memory array 1ba form a subbank B0 and memory array 1bb forms a subbank B1. In the 2-bit prefetch method, this SDRAM functions as 2-bank SDRAM. Banks A and B can be driven to the active and inactive states independently of each other. Designation of the bank is performed by a bank address which is applied simultaneously with a command.
For memory array 1aa, there are arranged an X-decoder group 2aa which is made active when a bank address signal Bx is active, and decodes row address signal (bits) X0-Xj (X0-j) to drive an addressed row in memory array 1aa to the selected state, a sense amplifier group 3aa which is made active when a sense amplifier activating signal .phi.SAA is active, to sense, amplify and latch data in the memory cells connected to the selected row in memory array 1aa, and a Y-decoder group 4aa which is made active when a bank address signal BY is active, and decodes column address signal (bits) YE0-YEk (YE0-k) to select an addressed column in memory array 1aa. The memory cell on the column selected by Y-decoder group 4aa is coupled to an internal data bus 5aa. Bank address signal BX is a bank address signal which is applied simultaneously with the active command or a precharge command instructing return to the precharge state. Bank address signal BY is a bank address signal which is applied simultaneously with the read command or the write command.
For memory array 1ab, there are arranged an X-decoder group 2ab which is made active when bank address signal BX is active, and decodes row address signal X0-Xj to drive an addressed row (word line) in memory array 1ab to the selected state, a sense amplifier group 3ab which is made active when sense amplifier activating signal .phi.SAA is active, to sense and amplify data of the memory cells in the selected row in memory array 1ab, and a Y-decoder group 4ab which is made active when bank address signal BY is active, and decodes column address signal YO0-YOk to select an addressed column in memory array 1ab. The memory cell on the column selected by Y-decoder group 4ab is coupled to internal data bus 5ab.
For memory array 1ba, there are arranged an X-decoder group 2ba which is made active when a bank address signal /BX is active, and decodes address signal X0-Xj to drive the addressed row in memory array 1ba to the selected state, a sense amplifier group 3ba which is made active when sense amplifier activating signal .phi.SAB is active, to sense, amplify and latch the data of memory cells connected to the selected row in memory array 1ba, and Y-decoder group 4ba which is made active when a bank address signal /BY is active, and selects an addressed column in memory array 1ba. Bank address signal /BX is complementary to bank address signal BX. Bank address signal /BY is complementary to bank address signal BY. The memory cell on the column in memory array 1ba selected by Y-decoder group 4ba is coupled to internal data bus 5ba.
For memory array 1bb, there are arranged an X-decoder group 2bb which is made active when bank address signal /BX is active, and decodes row address bits X0-Xj to drive the addressed row in the memory array 1bb to the selected state, a sense amplifier group 3bb which is made active when sense amplifier activating signal .phi.SAB is active, to sense, amplify and latch the data of memory cells on the selected row in memory array 1bb, and a Y-decoder group 4bb which is made active when bank address signal /BY is active, and decodes column address signal YO0-YOk to select the addressed column in memory array 1bb. The memory cell on the column selected by Y-decoder group 4bb is coupled to internal data bus 5bb.
The X-decoder groups, sense amplifier groups and Y-decoder groups described above each have the name of "group", because the X-decoder group includes X-decoders arranged corresponding to the rows, respectively, the sense amplifier group has sense amplifiers arranged corresponding to the columns in the corresponding memory array, respectively, and the Y-decoder group includes Y-decoders arranged corresponding to the columns, respectively.
In memory arrays 1aa and 1ab, selection of the memory cells is concurrently performed in accordance with bank address signals BX and BY, respectively. In memory arrays 1ba and 1bb, selection is concurrently performed in accordance with bank address signals /BX and /BY, respectively.
For writing data into memory arrays 1aa and 1ab, there are provided an input buffer 7a which is coupled to a data I/O terminal 6, and is activated in accordance with activation of an input buffer activating signal .phi.DBA to take in data supplied from data I/O terminal 6, a selector 8a for selecting paths for transferring write data applied from input buffer 7a in accordance with a select signal .phi.SEA, a write register 9aa which stores data applied from selector 8a in response to activation of a register activating signal .phi.RWA0, a write register 9ab which is provided for memory array 1ab, and takes in and latches data applied from selector 8a when register activating signal .phi.RWA1 is active, a write buffer 10aa which is provided corresponding to memory array 1aa, and is activated to amplify write data from write register 9aa for transmission onto internal data bus 5aa when write buffer activating signal .phi.WBA0 is active, and a write buffer 10ab which is provided corresponding to memory array 1ab, and is activated to amplify data stored in write register 9ab for transmission onto internal data bus 5ab when write buffer activating signal .phi.WBA1 is active. For internal data buses 5aa and 5ab, there is provided an equalize circuit 11a which is made active when equalize instructing signal .phi.WEQA is active, and sets internal data buses 5aa and 5ab to a predetermined potential level.
For memory arrays 1ba and 1bb, there are likewise provided an input terminal 7b which is coupled to data I/O terminal 6, and successively takes in data from data I/O terminal 6 to produce internal write data when an input buffer activating signal .phi.DBB is active, a selector 8b which selects data transfer paths from input buffer 7b in accordance with select signal .phi.SAB, write registers 9ba and 9bb which store data transferred from selector 8b in accordance with register activating signals .phi.RWB0 and .phi.RWB1, respectively, and write buffers 10ba and 10bb which amplify data stored in write registers 9ba and 9bb for transmission onto internal data buses 5ba and 5bb when write buffer activating signals .phi.WBB0 and .phi.WBB1 are active, respectively. For internal data buses 5ba and 5bb, there is provided an equalize circuit 11b which is activated to equalize internal data buses 5ba and 5bb to a predetermined potential when equalize instructing signal .phi.WEQB is active.
FIG. 40 schematically shows a structure of peripheral circuitry generating various internal signals shown in FIG. 39. In FIG. 40, the peripheral circuitry includes a control signal generating circuit 13 which takes in external control signals ext/RAS, ext/CAS, ext/OE and ext/WE, which are applied to input terminals 12a, 12b, 12c and 12d, respectively, in synchronization with rising of clock signal CLK, and generates internal control signals .phi.xa, .phi.ya, .phi.W, .phi.O, .phi.R and .phi.C in accordance with the states of these external control signals, respectively. Signal ext/OE is an output enable signal. When signal ext/OE is active, the output buffer (not shown) is enabled. When output enable signal ext/OE is inactive, the output buffer is in an output high impedance state. Clock signal CLK is a clock signal which is internally produced in accordance with external clock signal extCLK.
A signal .phi.xa is activated to instruct take-in of the row address signal when the active command is applied. Signal .phi.ya is activated when the read or write command is applied, and instructs take-in of the column address signal. Signal .phi.W is activated when the write command is applied, and instructs data writing. Signal .phi.O is activated when the read command is applied, and instructs data reading. Signal .phi.R is activated when the active command is applied, and activates circuits related to the row selection. Signal .phi.C is activated when the read or write command is applied, and activates column related circuits, i.e., circuits related to the column selection and data input/output.
The peripheral circuitry further includes an X-address buffer 14 which is responsive to activation of row address take-in instructing signal .phi.xa for taking in external address signal extA0-Ai (A0-i) and generating internal row address signal (bits) X0-Xj (X0-j) and bank address signal BX, a Y-address buffer 15 which is activated to take in external address signal extA0-i and generate the internal column address signal when column address take-in instructing signal .phi.ya is active, and a Y-address operation circuit 16 which operates in synchronization with clock signal CLK to change the internal column address signal applied from Y-address buffer 15 in accordance with a predetermined sequence, with the internal column address signal as a leading address, and produces even-numbered column address signal YE0-YEk (YE0-k), odd-numbered column address signal YO0-YOk (YO0-k) and a bank address signal BY. This Y-address operation circuit 16 includes a burst address counter, and changes the column address signal every two clock cycles.
The peripheral circuitry further includes a clock counter 17 which counts internal clock signal CLK in accordance with activation of column-related activating signal .phi.C, and generates a count-up signal at a predetermined timing in accordance with the counted value, and a control signal generating circuit 18 which receives the count-up signal of clock counter 17, bank address signals BX and BY, and lowest bit Y0 of the column address signal, and produces various internal control signals .phi.WBB0, .phi.WBB1, .phi.WBA0, .phi.WBA1, .phi.RWB0, .phi.RWB1, .phi..phi.RWA0, .phi.RWA1, .phi.SEA, .phi.SEB, .phi.DBA, .phi.DBB, .phi.WEQA and .phi.WEQB. In accordance with bank address signals BX and BY, the control signals for the designated bank are activated. The lowest column address signal bit Y0 is used for representing which one of the two memory arrays included in one bank is to be accessed first. Clock counter 17 includes a counter which counts the CAS latency and the burst length, and generates the count-up signal at a predetermined timing in accordance with the designated operation mode. A data write operation of the SDRAM shown in FIGS. 39 and 40 will be described below with reference to a timing chart of FIG. 41.
Before clock cycle #0 shown in FIG. 41, the active command is already applied, and certain rows are already driven to the selected state in memory arrays 1aa and 1ab shown in FIG. 39.
In clock cycle #0, column address strobe signal /CAS and write enable signal /WE are both set to L-level (while row address strobe signal /RAS is at H-level), and the write command is applied. Following assumptions are made. When this write command is applied, bank address BA designates bank A, bank address signal BX is activated, the lowest bit Y0 of address signal (Address) is 0, and memory array 1aa is designated. When the write command is applied, control signal generating circuit 40 shown in FIG. 40 drives column-related activating signal .phi.C to the active state in accordance with the write command, and the clock counter 17 is activated. Y-address buffer 15 takes in the externally applied column address signal in accordance with column address take-in instructing signal .phi.ya, and Y-address operation circuit 16 generates internal address signals (bits) YE0-YEk and YO0-YOk. Control signal generating circuit 18 successively activates the control signals for bank A including memory arrays 1aa and 1ab in accordance with bank address signal BY and the lowest address bit Y0.
For memory arrays 1aa and 1ab, Y-decoder groups 4aa and 4ab are activated to decode applied internal column address signals YE0-YEk and YO0-YOk, and select the corresponding columns to connect them to internal data buses 5aa and 5ab, respectively.
The input buffer 7a is activated to take in externally applied write data D0. Selector 8a first stores internal write data in write register 9aa in accordance with the lowest address signal bit Y0. Therefore, data D0 applied in first clock cycle #0 is stored in write register 9aa. Write data D1 applied in next clock cycle #1 is stored in write register 9ab.
For a period from clock cycle #0 to clock cycle #1, write buffer activating signal .phi.WBA0 is active, so that write buffer 10aa transmits write data onto internal data bus 5aa in accordance with data stored in write register 9aa. In clock cycle #1, write buffer 10ab is activated in accordance with write buffer activating signal .phi.WBA1, and drives internal data bus 5ab in accordance with data stored in write register 9ab. After data of 2 bits is written into memory arrays 1aa and 1ab, write buffers 10aa and 10ab are deactivated, and equalize circuit 11a equalizes internal data buses 5aa and 5ab.
In a next clock cycle #2, values of column address signals YE0-YEk and YO0-YOk from Y-address operation circuit 16 shown in FIG. 40 are changed, so that different columns are selected. External write data D2 and D3 applied in clock cycles #2 and #3 are stored in write registers 9aa and 9ab in accordance with select signal .phi.SEA, respectively. Then, write buffer 10aa is activated in response to activation of write buffer activating signal .phi.WBA0, and transmits write data onto internal data bus 5aa. In subsequent clock cycle #3, write buffer 10ab is activated in response to activation of write buffer activating signal .phi.WBA1, and transmits write data onto internal data bus 5ab. If the burst length is 4, data writing stops in accordance with the count-up signal from clock counter 17 after writing of four data D0-D3 is completed.
According to the data writing in this 2-bit prefetch method, both write buffers 10aa and 10ab are simultaneously made active, and two bits of data are simultaneously written in each of clock cycles #1 and #3. Y-decoder groups 4aa and 4ab are supplied with the same column address signal, and simultaneously perform the column select operation. Therefore, two clock cycles can be utilized for an operation from column selection to data writing. In memory array 1ab, data D1 which is externally applied in clock cycle #1 is transmitted onto the selected column of memory array 1ab in the same clock cycle #1. However, the column select operation has started in clock cycle #0, and two clock cycles can be utilized for an operation from the column selection to the actual data writing. Therefore, even in the case that external clock signal extCLK has a high frequency and a fast operation is performed, data writing can be performed with a sufficient margin.
FIG. 42 shows a structure of a data writing portion in an SDRAM of a pipelined type. FIG. 42 shows a structure of a portion related to data writing of 1 bit. Similarly to the SDRAM shown in FIG. 39, the SDRAM shown in FIG. 42 includes four memory arrays 1aa, 1ab, 1ba and 1bb. Memory arrays 1aa and 1ab form bank A, and memory arrays 1ba and 1bb form bank B. Similarly to the structure shown in FIG. 39, X-decoder groups 2aa, 2ab, 2ba and 2bb, sense amplifier groups 3aa, 3ab, 3ba and 3bb, and Y-decoder groups 4aa, 4ab, 4ba and 4bb are provided for memory arrays 1aa, 1ab, 1ba and 1bb, respectively. These structures are the same as those in the SDRAM of the 2-bit prefetch type shown in FIG. 39.
For writing data into bank A, there are provided an input buffer 7a which is coupled to data I/O terminal 6 and takes in applied data in response to activation of input buffer activating signal .phi.DBA, a write register 9a which takes in and latches data applied from input buffer 7a in response to activation of register activating signal .phi.RWA, and a write buffer 10a which amplifies the data applied from write register 9a for transmission onto internal data bus 5a in response to activation of write buffer activating signal .phi.WBA. Internal data bus 5a is provided commonly for memory arrays 1aa and 1ab.
For bank B, there are provided an input buffer 7b which is coupled to data I/O terminal 6 and takes in applied data in response to activation of input buffer activating signal .phi.DBA, a write register 9b which takes in and latches data applied from input buffer 7b in response to activation of register activating signal .phi.RWB, and a write buffer 10b which amplifies the data stored in write register 9b for transmission onto internal data bus 5b in response to activation of write buffer activating signal .phi.WBB. Internal data bus 5b is provided commonly for memory arrays 1ba and 1bb.
FIG. 43 schematically shows a structure of an internal signal generating portion in the SDRAM of the pipelined type shown in FIG. 42. An internal control signal generating circuit shown in FIG. 43 differs from the internal control signal generating circuit shown in FIG. 40 in a Y-address operation circuit 26 which generates internal column address signals YE0-YEk and YO0-YOk as well as bank address signal BY, and a control signal generating circuit 28 generating internal data write and transfer control signals. Y-address operation circuit 26 alternately activates even-numbered column address signal YE0-YEk and odd-numbered column address signal YO0-YOk every clock cycle.
Control signal generating circuit 28 operates in accordance with bank address signals BX and BY, and activates the control signals applied to the selected bank in accordance with a predetermined sequence. Selection of the memory cell for data writing is performed by internal column address signals YE0-YEk and YO0-YOk from Y-address operation circuit 26. The internal column address signals are alternately activated every clock cycle. Data write operation of the SDRAM of the pipelined type shown in FIGS. 42 and 43 will be described below with reference to a timing chart of FIG. 44.
Column address strobe signal /CAS and write enable signal /WE are set to L-level at the rising edge of external clock signal extCLK in clock cycle #1, and the write command is applied. Simultaneously with this write command, bank address signal BA is applied, and memory bank A (memory arrays 1aa and 1ab) is designated. At the same time, an even-numbered address is designated by externally applied address signal Address. Input buffer 7a is activated in accordance with activation of input buffer activating signal .phi.DBA, and takes in data D0, which is applied to data I/O terminal 6 for transference to write register 9a. Write register 9a takes in applied data in response to activation of register activating signal .phi.RWA, and is set to the latching state in response to deactivation of the signal .phi.RWA. When write register 9a attains the latching state, write buffer activating signal .phi.WBA is then activated, and write buffer 10a amplifies the data latched in write register 9a for transmission onto internal data bus 5a.
In memory array 1aa, Y-decoder group 4aa performs the column selection in accordance with internal column address signal YE0-YEk from Y-address operation circuit 26, and couples the selected column to internal data bus 5a. Thereby, data D0 is written into the selected memory cell in memory array 1aa. In parallel with this data writing, data D1 applied in the next clock cycle #2 is transferred and taken into write register 9a via input buffer 7a. Write register 9a is not yet in the latching state, and does not apply this data to write buffer 10a yet.
In clock cycle #2, Y-decoder group 4ab performs column selection in memory array 1ab, and the column thus selected is coupled to internal data bus 5a in accordance with internal column address signal YO0-YOk.
When write register 9a attains the latching state, write buffer 10a is activated again in response to activation of write buffer activating signal .phi.WBA, and transmits write data onto internal data bus 5a to write the data into the selected column (represented by CSL) in memory array 1ab. Thereby, data D1 is written into memory array 1ab.
Data D2 and D3 applied in following clock cycles #3 and #4 are successively written respectively into the selected columns in memory arrays 1aa and 1ab through input buffer 7a, write register 9a and write buffer 10a.
A write register 9a for latching data is arranged between input buffer 7a and write buffer 10a. In parallel with data writing into the memory array by write buffer 10a, write data can be transferred from input buffer 7a to write register 9a. Even in the case that a long time is required for transferring data from input buffer 7a to write buffer 10a, therefore, transfer of write data can be performed utilizing a time for data writing by the write buffer, so that the data transfer time can be effectively hidden by this data writing time, and fast data transfer is allowed.
In the SDRAM of this pipelined type, however, the column select operations in memory arrays 1aa and 1ab must be alternately performed every clock cycle, if bank A is selected. If bank B is designated, the operations are alternately performed in memory arrays 1ba and 1bb. Therefore, only one cycle can be utilized for operations from the column selection to writing of data into the selected column, resulting in such disadvantages that data cannot be written with a sufficient margin if external clock signal extCLK is fast, and the operation frequency cannot be increased as compared with the 2-bit prefetch type.
The SDRAM of the pipelined type internally performs the data transfer in a pipelined manner, and efficiently utilizes the clock cycle for performing data writing. In this SDRAM of the pipelined type, however, it is necessary to select and couple the column to the write buffer at each clock cycle. If the clock cycle is short, therefore, there is no time margin for connecting the selected column to the write buffer. Therefore, this SDRAM is not suitable to a fast operation (because internal data bus lines, i.e., local I/O bus is equalized after completion of writing of 1-bit data). In this SDRAM of the pipelined type, however, only one of the memory cell columns is selected in each clock cycle, and only one write buffer (per one I/O terminal) is activated, so that the power consumption is advantageously small. Therefore, the SDRAM of the pipelined type is used in a system using a low-speed clock signal CLK of, e.g., 66 MHz.
In the SDRAM of the prefetch type, two bits are prefetched, and memory cell data is written into the selected column during two clock cycles. Therefore, two clock cycles can be utilized for operations from the column selection to the connection of the selected column to the write buffer, and data writing can be performed with a sufficient margin even if the clock cycle is short. In the SDRAM of this 2-bit prefetch type, however, column selection is performed simultaneously in two memory arrays, and two write buffers are simultaneously activated, so that a current consumption is large. Therefore, in the case that this SDRAM of the 2-bit prefetch type is used in a system using a slow clock, a period of the clock cycle is long, and therefore the internal data bus is driven to the potential level corresponding to the write data for a long period, resulting in increase in current consumption. Accordingly, the SDRAM of the 2-bit prefetch type is used in a system performing a fast operation, e.g., at 100 MHz or 200 MHz.
The SDRAMs of the pipelined type and the 2-bit prefetch type have different internal structures, and therefore employ different chip structures. This results in increase in number of the types of products and complicated management by a manufacturer.
For overcoming the above problem, a structure, in which one of the pipelined type and the 2-bit prefetch type is selected by a bonding option in accordance with a data bit width, has been disclosed, for example, in "2.5 ns clock access 250 MHz 256 Mbits SDRAM having a synchronous mirror delay" by Saeki et al., in a lecture No. P23 in Transactions of ISSCC 96. Another structure in which one of a 2-bit prefetch type and a pipeline write type is selected by a bonding pad is also disclosed in Japanese Patent Laying-Open No. 7-169263 (1995).
According to the structure, in which the pipelined type and the 2-bit prefetch type are selectively employed by the bonding option, the same chip internal structure can be employed, and the chips of the same structure can be used to form selectively the SDRAM of the prefetch type and the SDRAM of the pipelined type in the final stage.
In this case, however, the data transfer method is set by the bonding option, and the data transfer type of the product, i.e., SDRAM is fixed to either the 2-bit prefetch type or the pipelined type. Therefore, a user selects either the SDRAM of the 2-bit prefetch type or the SDRAM of the pipelined type in accordance with the system application. However, if it becomes necessary to change the clock speed, for example, due to change in system specifications to be actually used, the SDRAM must be entirely changed in accordance with the specification change, so that the specifications cannot be changed easily.
Even in the case that change in clock speed due to, e.g., change in system specifications is not required, a user must select the SDRAMs in accordance with the intended clock speed, and therefore must accurately manage the purchased products at much expense in time and effort. If a pipelined SDRAM of a low-speed version is used in a high-speed system, it may be impossible to construct a processing system which can operate accurately. Therefore, a user must always recognize the product types of SDRAMs to be used in accordance with the processing system speed, and therefore must exercise extra care in using the products.